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HD404639R Series
4-Bit Single-Chip Microcomputer
Rev. 6.0 Sept. 1998 Description
The HD404639R Series is a member of the HMCS400-series microcomputers designed to increase program productivity with large-capacity memory. The HD404639R Series, completely compatible with the HD404639 Series, reduces current dissipation in half and includes a high-speed version. Each microcomputer has a high-precision dual-tone multi frequency (DTMF) generator, four timers, two serial interfaces, voltage comparator, input capture circuit, 32-kHz oscillator for clock, and four low-power dissipation modes. The HD404639R Series includes 5 chips: the HD404638R and HD40A4638R with 8-kword ROM; the HD404639R and HD40A4639R with 16-kword ROM; the HD407A4639R with 16-kword PROM. HD40A4638R, HD40A4639R, HD407A4639R are high-speed versions (minimum instruction cycle time: 0.5 s). The HD407A4639R is a PROM version ZTATTM microcomputer. A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTATTM version is 27256-compatible.) ZTAT TM : Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd.
Features
* 8,192-word x 10-bit ROM (HD404638R, HD40A4638R) * 16,384-word x 10-bit ROM (HD404639R, HD40A4639R, HD407A4639R) * 1,152-digit x 4-bit RAM * 61 I/O pins and 7 dedicated input pins 12 high-current output pins: Eight 15-mA sinks (a maximum of 7 pins can be used at the same time) and four 10-mA sources * Four timer/counters * Eight-bit input capture circuit * Three timer outputs (including two PWM outputs) * Two event counter inputs (including one double-edge function) * Two clock-synchronous 8-bit serial interfaces
HD404639R Series
* Comparator (4 channels) * On-chip DTMF generator: fOSC = 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz (7.16 MHz and 8 MHz are only available for HD40A4638R, HD40A4639R and HD407A4639R) * Built-in oscillators Main clock: Ceramic oscillator or crystal (an external clock is also possible) Subclock: 32.768-kHz crystal * Eleven interrupt sources Five by external sources, including three double-edge function Six by internal sources * Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time: 1 s (fOSC = 4 MHz at 1/4 division ratio), 0.5 s (fOSC = 8 MHz at 1/4 division ratio) 1/4, 1/8, 1/16, or 1/32 division ratio can be selected * Operation voltage 2.7 V to 6.0 V (HD404638R, HD404639R, HD40A4638R, HD40A4639R) 2.7 V to 5.5 V (HD407A4639R) With VCC = 2.2 V to 6.0 V, watch mode can be supported, and instructions can be executed in subactive mode (not applicable to the HD407A4639R). * Two operating modes MCU mode MCU/PROM mode (HD407A4639R)
Ordering Information
Type Mask ROM Instruction Cycle Time (s) 1 (fOSC = 4 MHz at 1/4 division ratio) Product Name HD404638R Model Name HD404638RF ROM (Words) 8,192 Package 80-pin plastic QFP (FP-80B)
HD404639R 0.5 (f OSC = 8 MHz at1/4 HD40A4638R division ratio) HD40A4639R ZTATTM 0.5 (f OSC = 8 MHz at 1/4 HD407A4639R division ratio)
HD404639RF HD40A4638RF HD40A4639RF
16,384 8,192 16,384
HD407A4639RF 16,384
2
HD404639R Series
Pin Arrangement
VTref VCC TONER TONEC SEL RC 0 RB 3 RB 2 RB 1 RB 0 RA 3 RA 2 RA 1 RA 0 R9 3 R9 2 80 7978 7776 757473727170 69686766 65 RD0 /COMP0 RD1 /COMP1 RD2 /COMP2 RD3 /COMP3 RE0 /VC ref TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 R9 1 R9 0 R8 3 R8 2 R8 1 R8 0 R7 3 R7 2 R7 1 R7 0 R6 3 R6 2 R6 1 R6 0 R5 3 /SO2 R5 2 /SI 2 R5 1 /SCK2 R5 0 R4 3 /SO1 R4 2 /SI 1 R4 1 /SCK1 R4 0 /EVND R3 3 /EVNB R3 2 /TOD FP-80B 25 2627 2829 303132333435 36373839 40 D12 /STOPC D13 /INT0 R00 /INT1 R01 /INT2 R02 /INT3 R03 /INT4 R10 R11 R12 R13 R20 R21 R22 R23 R30 /TOB R31 /TOC (Top view)
3
HD404639R Series
Pin Description
Item Power supply Test Reset Oscillator Symbol VCC GND TEST RESET OSC 1 Pin Number I/O Function 79 12 6 9 7 -- -- I I I Applies power voltage Connected to ground Used for factory testing only: Connect this pin to VCC Resets the MCU Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator, crystal, or connect OSC 1 to an external oscillator circuit
OSC 2 X1 X2 Port D0-D 11
8 10 11 13-24
O I O I/O Input/output pins addressed by individual bits; pins D 4- D11 are high-current sink pins that can each supply up to 15 mA, D 0-D 3 are high-current source pins that can each supply up to 10 mA I Input pins addressable by individual bits Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open.
D12, D13 R0 0-RC0 RD0-RD3,RE0 Interrupt Stop clear Serial interface INT0, INT1, INT2-INT4 STOPC SCK 1, SCK 2 SI 1, SI 2 SO1, SO2 Timer EVNB, EVND DTMF TONER TONEC VT ref
25, 26 27-75 1-5 26-30 25 44, 48 45, 49 46, 50
I/O Input/output pins addressable in 4-bit units I I I Input pins addressable in 4-bit units Input pins for external interrupts Input pin for transition from stop mode to active mode
I/O Serial interface clock input/output pin I O O I O O -- I -- I Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event count input pins Output pin for DTMF row signals Output pin for DTMF column signals. Reference voltage pin for DTMF signals. Voltage conditions being V CC VTref GND Analog input pins for voltage comparator Reference voltage pin for inputting the threshold voltage of the analog input pin. Input pin for selecting system clock division rate after RESET input or after stop mode cancellation. 1/4 division rate: Connect it to V CC 1/32 division rate: Connect it to GND
TOB, TOC, TOD 39-41 42, 43 78 77 80
Voltage COMP0-COMP3 1-4 comparator VC ref Division rate SEL 5 76
4
HD404639R Series
Block Diagram
RESET TEST STOPC OSC 1 OSC 2 X1 X2 SEL VCC GND
System control
INT 0 INT 1 INT 2 INT 3 INT 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 D 12 D 13 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RA0 RA1 RA2 RA3 RB 0 RB 1 RB 2 RB 3 RC 0 RC port RD 0 RD 1 RD 2 RD 3 RE port RE 0 High-current source pins
External interrupt
RAM (1,152 x 4 bit)
Timer A
W (2 bit) X (4 bit)
D port
High-current sink pins
EVNB TOB
Timer B
TOC
Timer C
SPX (4 bit) Y (4 bit)
EVND TOD SI 1 SO 1 SCK 1 SI 2 SO 2 SCK 2 VCref COMP0 COMP1 COMP2 COMP3 VTref TONER TONEC
Timer D
Serial interface 2
Internal address bus
Internal data bus
Serial interface 1
SPY (4 bit)
ALU CPU ST CA (1 bit) (1 bit)
Comparator
DTMF
A (4 bit) B (4 bit) SP (10 bit)
Insruction decoder
PC (14 bit)
RD port
ROM (16,384 x 10 bit) (8,192 x 10 bit)
RB port RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port
5
HD404639R Series
Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and described below.
0
Vector address 15 16 Zero-page subroutine (64 words) 63 64 Pattern (4,096 words) 4095 4096 Program (8,192 words) 8191 8192 Program (16,384 words) For HD404639R, HD40A4639R, HD407A4639R $3FFF For HD404638R, HD40A4638R $1FFF $2000 $0FFF $1000 $003F $0040 $000F $0010
$0000
0 JMPL instruction 1 (Jump to RESET, STOPC routine) JMPL instruction 2 (Jump to INT0 routine) 3 JMPL instruction 4 (Jump to INT1 routine) 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B, INT2 routine) JMPL instruction (Jump to timer C, INT3 routine) JMPL instruction (Jump to timer D, INT4 routine) JMPL instruction (Jump to serial 1, serial 2 routine)
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
16383
Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF (HD404638R, HD40A4638R), $0000-$3FFF (HD404639R, HD40A4639R, HD407A4639R)): Used for program coding.
6
HD404639R Series
RAM Memory Map The MCU contains a 1,152-digit x 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows. RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01E, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface 1, serial interface 2, timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090-$2EF): Consists of 464 digits from $090 to $25F in two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $2EF is accessed without setting the bank register. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
7
HD404639R Series
0 RAM-mapped registers 64 80 Not used 144 $090 Memory registers (MR) $040 $050 $000 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 Interrupt control bits area
(PMRA) Port mode register A Serial mode register 1A (SM1A) Serial data register 1 lower (SR1L) Serial data register 1 upper (SR1U) Timer mode register A (TMA) Timer mode register B1 (TMB1) (TRBL/TWBL) Timer B (TRBU/TWBU) (MIS) Miscellaneous register Timer mode register C1 (TMC1) (TRCL/TWCL) Timer C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer D (TRDU/TWDU) (TMB2) Timer mode register B2 Timer mode register C2 (TMC2) Timer mode register D2 (TMD2) Compare control register (CCR) Compare data register (CDR) (CER) Compare enable register TG mode register (TGM) (TGC) TG control register Serial mode register 2A (SM2A) Serial mode register 2B (SM2B) Serial data register 2 lower (SR2L) Serial data register 2 upper (SR2U) Not used
*
Data (464 digits x 2) V = 0 (bank 0) V = 1 (bank 1)
608 Data (144 digits) 752 960 Not used Stack (64 digits) 1023
$260 $2F0 $3C0 $3FF
$090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) $25F
W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R W W W W W R/W R/W
Register flag area Port mode register B Port mode register C (PMRB) (PMRC) W W W W W W W W W W W W W W W W W W W W W W W R/W
Detection edge select register 1 (ESR1) Detection edge select register 2 (ESR2)
Note: * The data area has two banks: bank 0 (V = 0) to bank 1 (V = 1) R: Read only W: Write only R/W: Read/Write
Serial mode register 1B
(SM1B)
System clock select register 1 (SSR1)
System clock select register 2 (SSR2)
Two registers are mapped on the same area. 10 11
Not used Port D0 to D3 DCR Port D4 to D 7 DCR Port D8 to D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR Port RA DCR Port RB DCR Port RC DCR Not used V register
$000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03F
(DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) (DCRB) (DCRC)
Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E 15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
8
HD404639R Series
Bit 3
0
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
$000
IM0 (IM of INT0)
IF0 (IF of INT0)
RSP (Reset SP bit)
1
IMTA (IM of timer A)
IMTC (IM of timer C)
IMS1 (IM of serial interface 1)
IFTA (IF of timer A) IFTC (IF of timer C)
IFS1 (IF of serial interface 1)
IM1 (IM of INT1)
IMTB (IM of timer B) IMTD (IM of timer D)
IF1 (IF of INT1)
IFTB (IF of timer B)
IFTD (IF of timer D)
$001
2
$002
3
$003
Interrupt control bits area
Bit 3
32
DTON (Direct transfer on flag)
Bit 2
Bit 1
WDON (Watchdog on flag)
Bit 0
LSON (Low speed on flag) $020
Not used
33
RAME (RAM enable flag)
Not used
ICEF (Input capture error flag)
ICSF (Input capture status flag)
$021
34
IM3 (IM of INT3)
IMS2 (IM of serial interface 2)
IF3 (IF of INT3)
IFS2 (IF of serial interface 2)
IM2 (IM of INT2)
IM4 (IM of INT 4 )
IF2 (IF of INT2)
IF4 (IF of INT 4 )
$022
35
$023
IF: IM: IE: SP:
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD IE IM LSON IF ICSF ICEF RAME RSP WDON DTON Not used Allowed REM/REMD Allowed TM/TMD Allowed
Not executed Not executed Allowed Not executed in active mode Used in subactive mode Not executed
Allowed Allowed Not executed Allowed Not executed
Allowed Inhibited Inhibited Allowed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
HD404639R Series
Bit 3 $000 $003 PMRA $004 SM1A $005 SR1L $006 SR1U $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 CCR $016 CDR $017 CER $018 TGM $019 TGC $01A SM2A $01B SM2B $01C SR2L $01D SR2U $01E $020 $023 PMRB $024 PMRC $025 ESR1 $026 R03/INT4 D13/INT0 *5 Not used Not used *4 *2 *3 *2 *1 *2 R52/SI2 R41/SCK1 Bit 2 Bit 1 Bit 0 Interrupt control bits area R53/SO2 R42/SI1 R43/SO1
Serial transmit clock speed selection 1 Serial data register 1 (lower digit) Serial data register 1 (upper digit) Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) Timer B register (upper digit) SO1 PMOS control Interrupt frame period selection Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Not used Timer-B output mode selection Timer-C output mode selection Timer-D output mode selection Internal reference voltages level
Result of each analog input comparison *6 *7 TONER output frequency DTMF enable Not used
TONEC output frequency *8 *9 R51/SCK2 Not used
Serial transmit clock speed selection 2 *10 *11 SO PMOS control
2
Serial data register 2 (lower digit) Serial data register 2 (upper digit) Not used Register flag area R02/INT3 D12/STOPC R01/INT2 R40/EVND R00/INT1 R33/EVNB
INT3 detection edge selection INT2 detection edge selection
ESR2 $027 EVND detection edge selection INT4 detection edge selection *12 *13 Not used Not used SM1B $028 *14 *15 System clock selection SSR1 $029 System clock selection System clock division rate SSR2 $02A Not used DCD0 $02C DCD1 $02D Port D3 DCR Port D2 DCR Port D7 DCR Port D6 DCR Port D1 DCR Port D0 DCR Port D5 DCR Port D4 DCR
DCD2 $02E Port D11 DCR Port D10 DCR Port D9 DCR Port D8 DCR Not used DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR5 $035 DCR6 $036 DCR7 $037 DCR8 $038 DCR9 $039 DCRA $03A DCRB $03B DCRC $03C V $03F Port R0 3 DCR Port R0 2 DCR Port R0 1 DCR Port R0 0 DCR Port R13 DCR Port R1 2 DCR Port R1 1 DCR Port R1 0 DCR Port R2 3 DCR Port R2 2 DCR Port R2 1 DCR Port R2 0 DCR Port R3 3 DCR Port R3 2 DCR Port R3 1 DCR Port R3 0 DCR Port R4 3 DCR Port R4 2 DCR Port R4 1 DCR Port R4 0 DCR Port R5 3 DCR Port R5 2 DCR Port R5 1 DCR Port R5 0 DCR Port R6 3 DCR Port R6 2 DCR Port R6 1 DCR Port R6 0 DCR Port R7 3 DCR Port R7 2 DCR Port R7 1 DCR Port R7 0 DCR Port R8 3 DCR Port R8 2 DCR Port R8 1 DCR Port R8 0 DCR Port R9 3 DCR Port R9 2 DCR Port R9 1 DCR Port R9 0 DCR Port RA 3 DCR Port RA2 DCR Port RA 1 DCR Port RA0 DCR Port RB 3 DCR Port RB2 DCR Port RB 1 DCR Port RB0 DCR Not used Not used Not used Not used Not used Not used Not used Port RC0 DCR *16 Notes: 1. Timer-A/time-base 2. Auto-reload on/off 3. Pull-up MOS control 4. Input capture selection 5. Comparator switch 6. Reference voltage selection 7. Comparator selection 8. TONEC output control 9. TONER output control 10. SO 2 output control in idle states 11. Serial clock source selection 2 12. SO 1 output level control in idle states 13. Transmit clock source selection 1 14. 32-kHz oscillation stop 15. 32-kHz oscillation division ratio 16. Bank 0 to bank 1 selection
Figure 5 Special Function Register Area
10
HD404639R Series
Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0
Bit 3 1020 1021 1022 $3FF 1023 ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 -- -- 0 0 R/W V0
Not used Not used Not used
V0 0 1
Bank area selection Bank 0 is selected Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected.
Figure 7 Bank Register (V)
11
HD404639R Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Figure 8 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.
12
HD404639R Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1.
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HD404639R Series
Table 1 Initial Values After MCU Reset
Item Program counter Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask I/O Port data register Data control register Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0-DCD2) (DCR0-DCRC) Port mode register A Port mode register B Port mode register C bits 3, 1, 0 Detection edge select register 1 Detection edge select register 2 Timer/ counters, serial interface Timer mode register A (PMRA) (PMRB) Initial Value Contents $0000 1 $3FF 0 0 1 All bits 1 All bits 0 All bits 0 0000 0000 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C Disables edge detection Disables edge detection Refer to description of timer mode register A Refer to description of timer mode register B1 Refer to description of timer mode register B2 Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests Enables output at level 1 Turns output buffer off (to high impedance)
(PMRC3, PMRC1, 000 PMRC0) (ESR1) (ESR2) (TMA) 0000 0000 0000 0000 - - 00 0000 - 000 0000 0000
Timer mode register B1 (TMB1) Timer mode register B2 (TMB2) Timer mode register C1 (TMC1) Timer mode register C2 (TMC2) Timer mode register D1 (TMD1) Timer mode register D2 (TMD2)
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
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HD404639R Series
Item Timer/ counters, serial interface Serial mode register 1A Serial mode register 1B Serial mode register 2A Serial mode register 2B Prescaler S Prescaler W Timer counter A Timer counter B Timer counter C Timer counter D Timer write register B Timer write register C Timer write register D Octal counter Comparator Compare control register (CCR) Compare enable register (CER) Bit register Low speed on flag Watchdog timer on flag Direct transfer on flag Input capture status flag Input capture error flag Others Miscellaneous register System clock select register 1 bits 2-0 System clock select register 2 Bank register (LSON) (WDON) (DTON) (ICSF) (ICEF) (MIS) (SSR12- SSR10) (SSR2) (V) Abbr. (SM1A) (SM1B) (SM2A) (SM2B) (PSS) (PSW) (TCA) (TCB) (TCC) (TCD) Initial Value 0000 - - X0 0000 - 0X0 $000 $00 $00 $00 $00 $00 Contents Refer to description of serial mode register 1A Refer to description of serial mode register 1B Refer to description of serial mode register 2A Refer to description of serial mode register 2B -- -- -- -- -- -- -- -- -- -- Refer to description of voltage comparator Refer to description of voltage comparator Refer to description of operating modes Refer to description of timer C Refer to description of operating modes Refer to description of timer D Refer to description of timer D Refer to description of operating modes, and oscillator circuit Refer to description of operating modes, and oscillator circuit
(TWBU, TWBL) $X0 (TWCU, TWCL) $X0 (TWDU, TWDL) $X0 000 0000 0000 0 0 0 0 0 0000 000 0000 ---0
Refer to description of RAM memory map
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
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HD404639R Series
Status After Cancellation of Stop Mode by STOPC Input Status After Cancellation of Stop Mode by MCU Reset Status After all Other Types of Reset
Item Carry flag
Abbr. (CA)
Pre-stop-mode values are not guaranteed; Pre-stop-mode values must be initialized by program values are not guaranteed; values must be initialized by program
Accumulator B register W register X/SPX register Y/SPY register Serial data register RAM RAM enable flag
(A) (B) (W) (X/SPX) (Y/SPY) (SRL, SRU) Pre-stop-mode values are retained (RAME) 1 0 0 0
Port mode register C bit 2 (PMRC2) System clock select register 1 bit 3 (SSR13)
Pre-stop-mode values 0 are retained
Interrupts The MCU has 11 interrupt sources: five external signals (INT0 , INT1, INT 2 , INT3 , INT4 ), four timer/counters (timers A, B, C, and D), and two serial interfaces (serial interface 1, serial interface 2). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and INT 3, timer D and INT4, and serial interface 1 and serial interface 2. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3.
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HD404639R Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer A Timer B, INT2 Timer C, INT3 Timer D, INT4 Serial 1 and 2 Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Note: * The STOPC interrupt request is valid only in stop mode
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source INT0 Interrupt Control Bit IE IF0 IM0 IF1 IM1 IFTA IMTA IFTB IMTB + IF2 IM2 IFTC IMTC + IF3 IM3 IFTD IMTD + IF4 IM4 IFS1 IMS1 + IFS2 IMS2
. . . . . . . . . . .
INT1 1 0 1 * * * * *
Timer A 1 0 0 1 * * * *
Timer B or INT2 1 0 0 0 1 * * *
Timer C or Timer D or Serial 1 or INT3 INT4 Serial 2 1 0 0 0 0 1 * * 1 0 0 0 0 0 1 * 1 0 0 0 0 0 0 1
1 1 * * * * * *
Note: * Can be either 0 or 1. Their values have no effect on operation.
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HD404639R Series
$ 000,0 IE $ 000,2 IFO $ 000,3 IMO Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt $ 002,0 IFTB $ 002,1 IMTB Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC Timer D interrupt $ 003,0 IFTD $ 003,1 IMTD $ 003,2 Serial 1 interrupt IFS1 $ 003,3 IMS1 Note: $m,n is RAM address $m, bit number n. $ 022,0 IF2 INT2 interrupt $ 022,1 IM2 $ 022,2 IF3 INT3 interrupt $ 022,3 IM3 $ 023,0 IF4 $ 023,1 IM4 $ 023,2 Serial 2 interrupt IFS2 $ 023,3 IMS2 INT4 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address
INT0 interrupt
Vector address
Timer A interrupt
Figure 9 Interrupt Control Circuit
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HD404639R Series
Instruction cycles 1 2 3 4 5 6
Instruction execution *
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 10 Interrupt Processing Sequence
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HD404639R Series
Power on
RESET = 1? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Accept interrupt
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer-A interrupt? No
PC $0008
Yes
Timer-B/INT2 interrupt? No
PC $000A
Yes
Timer-C/INT3 interrupt? No
PC $000C
Yes
Timer-D/INT 4 interrupt? No
PC $000E
(Serial 1, serial 2 interrupt)
Figure 11 Interrupt Processing Flowchart
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HD404639R Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE 0 1 Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0, INT1, INT2-INT4): Five external interrupt signals. External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2-IF4 are set at the rising or falling edge of signals input to INT 2-INT 4, as listed in table 5. The INT2-INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023)
IF0-IF4 0 1 Interrupt Request No Yes
Detection edge selection register 1 (ESR1: $026) Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 1 0 W ESR11 0 0 W ESR10
ESR13 0
ESR12 0 1
INT3 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
ESR11 0
ESR10 0 1
INT2 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
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HD404639R Series
Detection edge selection register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
ESR21 0
ESR20 0 1
INT 4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 13 detection Edge Selection Register 2 (ESR2) External Interrupt Masks (IM0-IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0-IM4: $000, $001, $022, $023)
IM0-IM4 0 1 Interrupt Request Enabled Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA 0 1 Interrupt Request No Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8.
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HD404639R Series
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA 0 1 Interrupt Request Enabled Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB 0 1 Interrupt Request No Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB 0 1 Interrupt Request Enabled Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC 0 1 Interrupt Request No Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC 0 1 Interrupt Request Enabled Disabled (masked)
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HD404639R Series
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 13. Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD 0 1 Interrupt Request No Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD 0 1 Interrupt Request Enabled Disabled (masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15 Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)
IFS1, IFS2 0 1 Interrupt Request No Yes
Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3)
IMS1, IMS2 0 1 Interrupt Request Enabled Disabled (masked)
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HD404639R Series
Operating Modes
The MCU has five operating modes as shown in table 17. The operations in each mode are listed in tables 18 and 19. Transitions between operating modes are shown in figure 14. Table 17 Operating Modes and Clock Status
Mode Name Active Activation method Standby Stop Watch Subactive
SBY RESET instruction cancellation, interrupt request STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) System oscillator OP OP OP RESET input, interrupt request
INT0 or timer A STOP STOP instruction when instruction when interrupt request TMA3 = 0 TMA3 = 1 from watch mode when STOP/SBY LSON = 1 instruction in subactive mode (when direct transfer is not selected)
Status
Stopped OP *1
Stopped OP
Stopped OP
Subsystem OP oscillator Cancellation method RESET input, STOP/SBY instruction
RESET input, RESET input, RESET input, STOPC input in INT0 or timer A STOP/SBY stop mode interrupt request instruction
Notes: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of system clock select register 1 (SSR1: $029).
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HD404639R Series
Table 18 Operations in Low-Power Dissipation Modes
Function CPU RAM Timer A Timer B Timer C Timer D Serial interface 1, 2 DTMF Comparator I/O Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset Reset*
1
Watch Mode Retained Retained OP Stopped Stopped Stopped Stopped* Reset Stopped Retained
2
Standby Mode Retained Retained OP OP OP OP OP OP Stopped Retained
Subactive Mode OP OP OP OP OP OP OP Reset OP OP
Notes: OP implies in operation 1. Output pins are at high impedance. 2. Transmission/reception is activated if a clock is input in external clock mode. However, all interrupts stop.
Table 19 I/O Status in Low-Power Dissipation Modes
Output Standby mode, watch mode D0-D 11 D12-D 13 , RD0-RD3, RE 0 R0 0-RC1 Retained or output of peripheral functions High impedance Input enabled Retained -- Stop mode High impedance -- Input Active mode, subactive mode Input enabled Input enabled
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HD404639R Series
Reset by RESET input or by watchdog timer
Stop mode
(TMA3 = 0, SSR13 = 0)
RAME = 0 RESET1
RAME = 1 RESET2
STOPC
STOPC
Active mode STOP fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate Stop fcyc fcyc SBY Interrupt fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate fcyc fcyc fcyc
(TMA3 = 0)
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop Stop Stop
Standby mode
(TMA3 = 0, SSR13 = 1)
STOP
fOSC: fX: o CPU : o CLK : o PER :
Stop Stop Stop Stop Stop
Watch mode
(TMA3 = 1) (TMA3 = 1, LSON = 0)
fOSC: fX: o CPU : o CLK : o PER :
Oscillate Oscillate Stop fW fcyc
SBY Interrupt
fOSC: fX: o CPU : o CLK : o PER :
Oscillate Oscillate fcyc fW fcyc
STOP INT0, timer A*1
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop fW Stop
*3
Main oscillation frequency Suboscillation frequency for time-base fOSC/4 or fOSC/8 or fcyc: f OSC/16 or fOSC/32 (software selectable) fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU : System clock o CLK : Clock for time-base o PER : Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag
fOSC: fX:
Subactive mode fOSC: fX: o CPU : o CLK : o PER :
*2
STOP Stop Oscillate fSUB fW fSUB
*4
(TMA3 = 1, LSON = 1)
INT0, timer A*1
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop fW Stop
Notes: 1. 2. 3. 4.
Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1)
Figure 14 MCU Status Transitions
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HD404639R Series
Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15. Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of system clock select register 1 (SSR1: $029; operating: SSR13 = 0, stop: SSR13 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 41). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figures 17 and 18. Operation during mode transition is the same as that at standby mode cancellation (figure 15).
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HD404639R Series
Stop Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Standby Watch
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop
No
RESET = 1?
RESET = 1?
No
Yes No
STOPC = 0?
Yes
IF0 * IM0 = 1?
No
Yes Yes
IF1 * IM1 = 1?
No
Yes
IFTA * IMTA = 1?
No
IFTB * IMTB + IF2 * IM2 = 1?
Yes
No
IFTC * IMTC + IF3 * IM3 = 1?
RAME = 1
RAME = 0
Yes
No
IFTD * IMTD + IF4 * IM4 = 1?
Yes
No
IFS1 * IMS1 + IFS2 * IMS2 = 1?
Yes (SBY only) (SBY only) (SBY only) (SBY only)
No
(SBY only)
Yes
Restart processor clocks
Restart processor clocks Execute next instruction
No
IF = 1, IM = 0, and IE = 1?
Yes
Reset MCU
Execute next instruction
Accept interrupt
Figure 15 MCU Operation Flowchart
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HD404639R Series
Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres tRC (stabilization period)
Figure 16 Timing of Stop Mode Cancellation
Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the DTMF generator operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR12) of system clock select register 1 (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, CLK is applied to timer A and the INT0 circuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with t he interrupt strobe timing.
Note on Use: When the MCU is in watch mode or sub-active mode and if the high level period before the falling edge of INT0 is shorter than the interrupt frame or if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Therefore, the high or low level period of INT 0 must be held longer than the interrupt frame when the MCU is in watch mode or subactive mode.
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HD404639R Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation tRC
(During the transition from watch mode to active mode only) T: Interrupt frame length t RC : Oscillation stabilization period
T
T TX
Note : If the time from the fall of the INT0 signal until the interrupt is accepted and active mode is entered is TX, then TX will be in the following range : T + tRC TX 2T + tRC
Figure 17 Interrupt Frame
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3
MIS2
MIS1 0
MIS0 0
T *1
tRC* 1
Oscillation circuit conditions External clock input
Buffer control. Refer to figure 38.
0.24414 ms 0.12207 ms 0.24414 ms
*2
0 1 1
1 0 1
15.625 ms 62.5 ms Not used
7.8125 ms 31.25 ms
Ceramic oscillator Crystal oscillator --
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used.
Figure 18 Miscellaneous Register (MIS)
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HD404639R Series
Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode:
tRC < TD < T + tRC
STOP/SBY instruction execution MCU internal Subactive mode processing period (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T TD T: tRC: TD: Interrupt frame length Oscillation stabilization period Transition time
Oscillation stabilization time
Active mode
t RC
Figure 19 Direct Transition Timing Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by a STOPC input as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
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HD404639R Series
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 1 ? Yes RAME = 0
No
MCU operation cycle
Reset MCU
Figure 20 MCU Operating Sequence (Power On)
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HD404639R Series
MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Instruction execution
Yes
Yes
SBY/STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 21 MCU Operating Sequence (MCU Operation Cycle)
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HD404639R Series
Low-power mode operation cycle
IF = 1 and IM = 0?
No
Yes
Standby/Watch mode Stop mode
No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle For IF and IM operation, refer to figure 15.
Figure 22 MCU Operating Sequence (Low-Power Mode Operation)
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HD404639R Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 23. As shown in table 20, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. System clock select register 1 (SSR1: $029) and system clock select register 2 (SSR2: $02A) must be selected according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 24). Note: If the SSR10, SSR11, SSR22 and SSR23 setting does not match the oscillator frequency, the DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.
LSON 1/4 or 1/8 or 1/16 or 1/32 division circuit* 1
OSC2 OSC1
System fOSC oscillator
fcyc tcyc
Timing generator circuit
oCPU System clock selection oPER
CPU with ROM, RAM, registers, flags, and I/O
Peripheral function interrupt
fX
X1 X2
Subsystem oscillator
fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit*2 circuit TMA3
1/8 division circuit
fW tWcyc
Timing generator circuit
Time-base clock oCLK selection
Time-base interrupt
Notes: 1. 1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 1 and 0 of system clock select register 2 (SSR2: $02A). 2. 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (SSR1: $029).
Figure 23 Clock Generation Circuit
36
HD404639R Series
System clock select register 1 (SSR1: $029) Bit Initial value Read/Write Bit name 3 0 W SSR13 2 0 W SSR12 1 0 W SSR11 0 0 W SSR10
SSR13 0 1
32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode
SSR23 SSR22 0 0
SSR11 0
SSR10 0 1
System clock selection 400 kHz 800 kHz 2 MHz 4 MHz
1 SSR12 0 1 32-kHz oscillation division ratio selection fSUB = fX/8 fSUB = fX/4 1 1 0 1
0 1
Don't care Don't care 3.58 MHz 1 1 8 MHz
Don't care Don't care 7.16 MHz
Figure 24 System Clock Select Register 1 (SSR1)
GND
X2
X1
RESET
OSC2 OSC1 TEST GND
Figure 25 Typical Layouts of Crystal and Ceramic Oscillator
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HD404639R Series
The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A). The values of SSR20 and SSR21 are valid after the MCU enters watch mode (SSR22 and SSR23 are valid directly). The system clock must be stopped when the division ratio is to be changed. There are two ways for setting the division ratio of the system clock. * The division ratio is selected by setting SSR20 and SSR21 in active mode (at this time, the presetting values of SSR20 and SSR21 are valid). This causes the MCU to enter watch mode (system clock is stopped). When the MCU enters active mode from watch mode, the setting values of SSR20 and SSR21 become valid. * The division ratio can also be selected by setting SSR20 and SSR21 in subactive mode. This causes the MCU to enter active mode via watch mode, thus validating the setting values of SSR20 and SSR21 (so does the case of direct transition). After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be selected as 1/4 or 1/32 by setting the SEL pin level. * 1/4 division ratio: Connect SEL to VCC. * 1/32 division ratio: Connect SEL to GND. The division ratio of the subsystem clock can be selected as 1/4 or 1/8 by setting bit 2 (SSR12) of system clock select register 1 (SSR1: $029). SSR12 is valid directly after being set, but in order to change the value of SSR12, the MCU must be in active mode. If SSR12 is changed in subactive mode, the MCU will malfunction.
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HD404639R Series
System clock select register 2 (SSR2: $02A) Bit Initial value Read/Write Bit name 3 0 W SSR23 2 0 W SSR22 1 0 W SSR21 0 0 W SSR20
SSR23 0
SSR22 0 1
System clock selection Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz*2 3.58 MHz 8 MHz*2 7.16 MHz
SSR21 0
SSR20 0 1
System clock division ratio 1/4 division 1/8 division 1/16 division 1/32 division
*1
1
0 1
1
0 1
Notes: 1. The DTMF frequencies are not affected by the setting of the system clock division ratio. 2. Refer to system clock select register 1 (SSR1) of figure 24.
Figure 26 System Clock Select Register 2 (SSR2)
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HD404639R Series
Table 20 Oscillator Circuit Examples
Circuit Configuration External clock operation Circuit Constants
External oscillator
OSC 1
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND
Ceramic oscillator: CSB400P22 (Murata), CSB400P (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5%
Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA8.00MT (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20%
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HD404639R Series
Circuit Configuration Crystal oscillator (OSC1, OSC 2)
C1 OSC1 Crystal oscillator Rf OSC2 C2 GND L OSC1 C0 CS RS OSC2
Circuit Constants Rf = 1 M 20% C1 = C2 = 10-22 pF 20% Crystal: Equivalent to circuit shown below C0 = 7 pF max RS = 100 max f = 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, 8 MHz
Crystal oscillator (X1, X2)
C1 X1 Crystal oscillator X2 C2 GND L X1 C0 CS RS X2
Crystal: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF 20% RS: 14 k C0: 1.5 pF
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, X1, X2, and elements should be as short as possible, and must not cross other wiring (see figure 25). 3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to VCC and X2 must be open.
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HD404639R Series
Input/Output
The MCU has 61 input/output pins (D0-D11, R0 0-RC 0) and 7 input pins (D12, D13, RD0-RD3, RE 0). The features are described below. * A maximum current of 15 mA is allowed for each of the pins D 4 to D11 with a total maximum current of less than 105 mA. In addition, D0-D3 can each act as a 10-mA maximum current source. * Some input/output pins are multiplexed with peripheral function pins such as those for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R43/SO1 and R5 3/SO 2 pins can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Pins D0-D3 have built-in pull-down MOS, and other input/output pins have built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 27, programmable I/O circuits are listed in table 21, and I/O pin circuit types are shown in table 22. Table 21-1 Programmable I/O Circuits (with Pull-Up MOS)
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-up MOS 0 0 0 -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
Note: -- indicates off status.
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HD404639R Series
D4-D11, R port HLT VCC Pull-up MOS VCC Pull-up control signal MIS3
Buffer control signal DCD, DCR
Output data
PDR
Input data Input control signal
Figure 27-1 I/O Buffer Configuration (with Pull-Up MOS) Table 21-2 Programmable I/O Circuits (with Pull-Down MOS)
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-down MOS 0 0 0 -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- On 1 -- -- -- 1 0 -- On On 1 On -- --
Note: -- indicates off status.
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HD404639R Series
D0-D3 port Input control signal Input data
VCC
Buffer control signal DCD
Output data Pull-Down Mos Pull-down control signal
PDR
MIS3
HLT
Figure 27-2 I/O Buffer Configuration (with Pull-Down MOS)
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HD404639R Series
Table 22 Circuit Configurations of I/O Pins
I/O Pin Type Input/output pins Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal MIS3 DCD, DCR PDR
Pins D4-D 11 , R0 0-R0 3 R1 0-R1 3, R2 0-R2 3 R3 0-R3 3, R4 0-R4 2 R5 0-R5 2 R6 0-R6 3 R7 0-R7 3, R8 0-R8 3 R9 0-R9 3, RA 0-RA 3 RB 0-RB 3, RC0
Input control signal
D0-D 3
Input data
VCC
Buffer control signal
DCD
Output data
PDR MIS3
Pull-down control signal HLT
HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2, SM2B2 PDR
VCC
R4 3, R5 3
Output data Input data Input control signal
Input pins
Input data Input control signal
D12, D13 RD0-RD3, RE 0
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HD404639R Series
I/O Pin Type Peripheral Input/ function pins output pins Circuit
VCC HLT VCC Pull-up control signal MIS3
Pins SCK 1, SCK 2
Output data Input data
SCK1, SCK2
SCK1, SCK2
Peripheral Output function pins pins
VCC
HLT VCC Pull-up control signal MIS3
SO1, SO2
PMOS control signal Output data
MIS2, SM2B2 SO1, SO2
VCC
HLT VCC Pull-up control signal MIS3
TOB, TOC, TOD
Output data
TOB, TOC, TOD
Input pins
VCC HLT MIS3 PDR SI1, SI2, INT1, etc
SI 1, SI 2, INT1, INT2, INT3, INT4, EVNB, EVND
Input data
Input data
INT0, STOPC
INT0, STOPC
Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes.
D Port (D0-D13): Consist of 12 input/output pins and 2 input pins addressed by one bit. D0-D3 are highcurrent sources, D4-D11 are high-current sinks, and D12 and D 13 are input-only pins. Pins D0-D 11 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 28).
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HD404639R Series
Pins D 12 and D13 are multiplexed with peripheral function pins STOPC and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 29). R Ports (R0 0-RC0, RD0-RE0): 49 input/output pins and 5 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCRC: $030-$03C) that are mapped to memory addresses (figure 28). Pins R00-R03 are multiplexed with peripheral pins INT1-INT 4, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0-PMRB3) of port mode register B (PMRB: $024) (figure 30). Pins R30-R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 31, 32, and 33). Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 29). Pins R41-R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 34 and 36. Ports R51-R5 3 are multiplexed with peripheral function pins SCK 2, SI2, SO2, respectively. The function modes of these pins can be selected by individual pins, by setting bit 3 (SM2A3) of serial mode register 2A (SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 35 and 36). Ports RD 0-RD3 are multiplexed with peripheral function pins COMP0-COMP3, respectively. The function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018). Port RE 0 is multiplexed with peripheral function pin VCref. While functioning as VC ref , do not use this pin as an R port at the same time, otherwise, the MCU may malfunction. Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS transistor is provided for each input/output pin other than input-only pins D 12 and D 13. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 21 and figure 38). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k or pulled down to GND by their pull-down MOS transistors.
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HD404639R Series
Data control register DCD0 to DCD2 Bit Initial value Read/Write Bit name (DCD0 to 2: $02C to $02E) (DCR0 to C: $030 to $03C) 2 0 W 1 0 W 0 0 W
3 0 W
DCD03- DCD02- DCD01- DCD00- DCD23 DCD22 DCD21 DCD20 3 0 W 2 0 W 1 0 W 0 0 W
DCR0 to DCRB Bit Initial value Read/Write Bit name DCRC Bit Initial value Read/Write Bit name All Bits 0 1
DCR03- DCR02- DCR01- DCR00- DCRB3 DCRB2 DCRB1 DCRB0 3 -- -- 2 -- -- 1 -- -- 0 0 W
Not used Not used Not used DCRC0 CMOS Buffer On/Off Selection Off (high-impedance) On
Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8 DCR9 DCRA DCRB DCRC Bit 3 D3 D7 D11 R03 R13 R23 R33 R43 R53 R63 R73 R83 R93 RA3 RB3 -- Bit 2 D2 D6 D10 R02 R12 R22 R32 R42 R52 R62 R72 R82 R92 RA2 RB2 -- Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R51 R61 R71 R81 R91 RA1 RB1 -- Bit 0 D0 D4 D8 R00 R10 R20 R30 R40 R50 R60 R70 R80 R90 RA0 RB0 RC0
Figure 28 Data Control Registers (DCD, DCR)
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HD404639R Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W PMRC1 0 0 W PMRC0
PMRC3 PMRC2 *
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Note: PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value.
Figure 29 Port Mode Register C (PMRC )
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HD404639R Series
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 0 W PMRB3 2 0 W 1 0 W 0 0 W
PMRB2 PMRB1 PMRB0
PMRB0 0 1 PMRB1 0 1 PMRB2 0 1 PMRB3 0 1
R00/INT1 mode selection R00 INT1 R01/INT2 mode selection R01 INT2 R02/INT3 mode selection R02 INT3 R03/INT4 mode selection R03 INT4
Figure 30 Port Mode Register B (PMRB)
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 31 Timer Mode Register B2 (TMB2)
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HD404639R Series
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC TOC TOC TOC TOC PWM output R31 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1
Figure 32 Timer Mode Register C2 (TMC2)
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HD404639R Series
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD TOD TOD TOD TOD R32 PWM output Input capture (R32 port) R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1
1
Don't care Don't care Don't care
Figure 33 Timer Mode Register D2 (TMD2)
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HD404639R Series
Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
1
0 1
1
0
0 1
1
0 1
Figure 34 Serial Mode Register 1A (SM1A)
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HD404639R Series
Serial mode register 2A (SM2A: $01B) Bit Initial value Read/Write Bit name 3 0 W SM2A3 2 0 W SM2A2 1 0 W SM2A1 0 0 W SM2A0 Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
SM2A3 0 1
R51/SCK 2 mode selection R51 SCK2
SM2A2 0
SM2A1 0
SM2A0 0 1
SCK2 Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
1
0 1
1
0
0 1
1
0 1
Figure 35 Serial Mode Register 2A (SM2A)
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HD404639R Series
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W
PMRA2 PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1 PMRA2 0 1 PMRA3 0 1
R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1 R53/SO2 mode selection R53 SO2 R52/SI2 mode selection R52 SI2
Figure 36 Port Mode Register A (PMRA)
55
HD404639R Series
Compare enable register (CER: $018) Bit Initial value Read/Write Bit name 3 0 W CER3 2 0 W CER2 1 0 W CER1 0 0 W CER0
CER3 0
Digital/Analog selection Digital input mode: RD0 /COMP0 -RD3 /COMP3 operate as an R port. Analog input mode: RD0 /COMP0 -RD 3 /COMP3 operate as analog input. Reference voltage selection External input voltage Internal voltage
CER1 0 0 1 1
CER0 0 1 0 1
Analog input pin selection COMP0 COMP1 COMP2 COMP3
1
CER2 0 1
Figure 37 Compare Enable Register (CER)
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-up and pull-down MOS on/off selection Off On
MIS2 0 1
PMOS transistor on/off selection for pin R43/SO1 On Off
MIS1
MIS0
tRC selection. Refer to figure 18 in the operation modes section.
Figure 38 Miscellaneous Register (MIS)
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HD404639R Series
Prescalers
The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 23, and the prescalers output supply is shown in figure 39. The timers A-D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 23 Prescaler Operating Conditions
Prescaler Prescaler S Input Clock System clock (in active and standby mode), Subsystem clock (in subactive mode) 32-kHz crystal oscillation Reset Conditions MCU reset Stop Conditions MCU reset, stop mode, watch mode MCU reset, stop mode
Prescaler W
MCU reset, software
Subsystem clock
fX/8
Prescaler W
Timer A Timer B Timer C
fX/4 or fX/8
System clock
Clock selector
Prescaler S
Timer D Serial interface 1 Serial interface 2
Figure 39 Prescaler Output Supply
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HD404639R Series
Timers
The MCU has four timer/counters (A to D). * * * * Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer
Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers, whose functions are listed in table 24. The operating modes are selected by software. Table 24 Timer Functions
Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- means not available. Timer A Available Available -- Available Available -- -- -- -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- -- Available Available Available -- Timer C Available -- -- Available -- -- Available Available -- Available Available Available Available Timer D Available -- Available Available -- Available Available -- Available Available Available Available Available
Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 40.
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HD404639R Series
32.768-kHz oscillator 1/4 1/2 2 fW 1/2 t Wcyc Selector Internal data bus 59 Selector Clock Timer counter A (TCA) Overflow fW t Wcyc Prescaler W (PSW)
/2 /8 / 16 / 32
Timer A interrupt request flag (IFTA)
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Figure 40 Block Diagram of Timer A Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 41.
HD404639R Series
Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Don't care PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW Inhibited PSW and TCA reset 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Time-base mode Timer A mode
Notes: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur.
Figure 41 Timer Mode Register A (TMA)
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HD404639R Series
Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs) The block diagram of timer B is shown in figure 42.
Timer B interrupt request flag (IFTB) TOB Timer output control logic
Timer read register BU (TRBU) Timer read register BL (TRBL) Clock Timer counter B (TCB) Overflow
Timer output control
Selector
/2 /4 /8 / 32 / 128 / 512
EVNB System clock o PER
/ 2048
Timer write register BU (TWBU) Timer write register BL (TWBL)
Prescaler S (PSS) Free-running/ Reload control 3
Timer mode register B1 (TMB1)
2 Timer mode register B2 (TMB2)
Figure 42 Block Diagram of Timer B
Internal data bus 61
HD404639R Series
Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operations are basically the same as the free-running/reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 43. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low.
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HD404639R Series
Toggle output waveform (timers B, C, and D) Free-running timer
256 clock cycles Reload timer
256 clock cycles
(256 - N) clock cycles (256 - N) clock cycles
PWM output waveform (timers C and D) T x (N + 1)
TMC13 = 0 TMD13 = 0 T x 256
T TMC13 = 1 TMD13 = 1
T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 52 and 59) N: The value of the timer write register
Figure 43 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44. It is reset to $0 by MCU reset.
63
HD404639R Series
Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10
TMB13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R33/EVNB (external event input)
1
0 1
1
0
0 1
1
0 1
Figure 44 Timer Mode Register B1 (TMB1) * Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 45. It is reset to $0 by MCU reset.
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 45 Timer Mode Register B2 (TMB2)
64
HD404639R Series
* Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU) as shown in figures 46 and 47. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A) Bit Initial value Read/Write Bit name 3 0 W TWBL3 2 0 W TWBL2 1 0 W TWBL1 0 0 W TWBL0
Figure 46 Timer Write Register B Lower Digit (TWBL)
Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWBU3 W TWBU2 W TWBU1 W TWBU0
Figure 47 Timer Write Register B Upper Digit (TWBU) * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 48 and 49). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained.
Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBL3 R TRBL2 R TRBL1 R TRBL0
Figure 48 Timer Read Register B Lower Digit (TRBL)
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HD404639R Series
Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBU3 R TRBU2 R TRBU1 R TRBU0
Figure 49 Timer Read Register B Upper Digit (TRBU) * Port mode register C (PMRC: $025): Write-only register that selects R33/EVNB pin function as shown in figure 50. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W 1 0 W 0 0 W
PMRC2 PMRC1 PMRC0
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Figure 50 Port Mode Register C (PMRC)
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HD404639R Series
Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 51.
System reset signal Watchdog on flag (WDON) Watchdog timer control logic
Timer C interrupt request flag (IFTC)
TOC
Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Clock Timer counter C (TCC) Overflow
Selector
/2 /4 /8 /32 /128 /512 /1024 /2048
Timer write register CU (TWCU) Free-running /Reload control
3
System oPER clock
Timer write register CL (TWCL)
Prescaler S (PSS)
Timer mode register C1 (TMC1)
3
Timer mode register C2 (TMC2)
Figure 51 Block Diagram of Timer C
Internal data bus
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HD404639R Series
Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 43. Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F)
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HD404639R Series
* Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 52. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10
TMC13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMC12 0
TMC11 0
TMC10 0 1
Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 52 Timer Mode Register C1 (TMC1) * Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 53. It is reset to $0 by MCU reset.
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HD404639R Series
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 TMC21 0 0 0 R/W TMC20 TMC20 0 1 1 0 1 1 0 0 1 1 0 1 R31/TOC mode selection R31 TOC TOC TOC TOC TOC TOC TOC PWM output R31 port Toggle output 0 output 1 output Inhibited
Not used TMC22 TMC22 0
Figure 53 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) as shown in figures 54 and 55. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 54 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0
Figure 55 Timer Write Register C Upper Digit (TWCU)
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HD404639R Series
* Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures 56 and 57. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).
Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0
Figure 56 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0
Figure 57 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer
The block diagram for each operation mode of timer D is shown in figures 58 (A) and (B).
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HD404639R Series
Timer D interrupt request flag (IFTD) TOD Timer output control logic
Timer read register DU (TRDU)
Timer output control Timer read register DL (TRDL) Clock Timer counter D (TCD) Overflow
Selector EVND Edge detection logic /32 /2 /4 /8 oPER
/2048
/128
/512
Free-running/ Reload control 3
Timer write register DL (TWDL)
System clock
Prescaler S (PSS)
Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control
2 Edge detection selection register 2 (ESR2)
Figure 58 (A) Block Diagram of Timer D (Free-Running/Reload Timer)
72
Internal data bus
Timer write register DU (TWDU)
HD404639R Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Error control logic Timer D interrupt request flag (IFTD)
Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Input capture timer control Internal data bus 73 Timer counter D (TCD) Overflow
Selector
3 Timer mode register D1 (TMD1)
System clock
oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2)
Figure 58 (B) Block Diagram of Timer D (Input Capture Timer) Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010).
/2048
/128
/512
/32
/2
/4
/8
HD404639R Series
Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operations are basi cally the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00.
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HD404639R Series
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10
TMD13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMD12 0
TMD11 0
TMD10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R40/EVND (External event input)
1
0 1
1
0
0 1
1
0 1
Figure 59 Timer Mode Register D1 (TMD1)
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HD404639R Series
* Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset.
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD TOD TOD TOD TOD R32 PWM output Input capture (R32 port) R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1
1
Don't care Don't care Don't care
Figure 60 Timer Mode Register D2 (TMD2) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) as shown in figures 61 and 62. The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0
Figure 61 Timer Write Register D Lower Digit (TWDL)
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HD404639R Series
Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0
Figure 62 Timer Write Register D Upper Digit (TWDU) * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) as shown in figures 63 and 64. The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first.
Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0
Figure 63 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0
Figure 64 Timer Read Register D Upper Digit (TRDU) * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 50. It is reset to $0 by MCU reset. * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset.
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HD404639R Series
Detection edge selection register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
ESR21 0
ESR20 0 1
INT 4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 65 Detection Edge Select Register 2 (ESR2) Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 25. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle.
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HD404639R Series
Table 25 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N
Timer Write Register is Updated during Low PWM Output
Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
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HD404639R Series
Serial Communications Interface
The MCU has two channels of serial interface. The transfer and receive start instructions differ according to the serial interface channel, but other functions are the same. The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as follows. Serial interface 1 * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC1) Selector
Serial interface 2 * * * * * * Serial data register 2 (SR2L: $01D, SR2U: $01E) Serial mode register 2A (SM2A: $01B) Serial mode register 2B (SM2B: $01C) Port mode register A (PMRA: $004) Octal counter (OC2) Selector
The block diagram of the serial interface is shown in figure 66.
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HD404639R Series
Octal counter (OC1, OC2)
Serial interrupt request flag (IFS1, IFS2)
Idle control logic SO1 , SO2 I/O control logic SCK1 , SCK2 Clock Serial data register (SR1L/U, SR2L/U) Transfer control Internal data bus 81
SI1 , SI 2 Selector 1/2 1/2
Selector
3 Serial mode register 1A, 2A (SM1A, SM2A)
System clock
oPER
Prescaler S (PSS)
/2048
/128
/512
/32
/2
/8
Serial mode register 1B, 2B (SM1B, SM2B)
Figure 66 Block Diagram of Serial Interface Serial Interface Operation Serial Interface Operation Selecting and Changing the Operating Mode: Tables 26 (A) and 26 (B) list the serial interfaces' operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), serial mode register 1A (SM1A: $005), and serial mode register 2A (SM2A: $01B) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A; and to change the operating mode of serial interface 2, always initialize the serial interface internally by writing data to serial mode register 2A. Note that serial interface
HD404639R Series
1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data to serial mode register 2A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R5 1/SCK 2 pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R42/SI1, R4 3/SO 1, R5 2/SI 2, and R5 3/SO 2 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2 (SR2L: $01D, SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. Receive data of serial interface 2 is obtained by reading the contents of serial data register 2. The serial data is shifted by each serial interface transmit clock and is input from or output to an external system. The output level of the SO1 and SO2 pins is invalid until the first data of each serial interface is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by a dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The octal counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at the rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interface 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial interface 2 interrupt request flag (IFS2: $023, bit 2) for serial interface 2 are set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0-SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 27. When the prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SM2A0-SM2A2) of serial mode register 2A (SM2A: $01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C). Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that compares serial mode register 2A with the accumulator. Serial mode register 2A is a read-only register, so $0 can be read.
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Table 26 (A) Serial Interface 1 Operating Modes
SM1A Bit 3 1 PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Table 26 (B) Serial Interface 2 Operating Modes
SM2A Bit 3 1 PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Table 27 Transmit Clock (Prescaler Output)
SM1B/ SM2B Bit 0 0 SM1A/ SM2A Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
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HD404639R Series
Operating States: Serial interface 1 has the following operating states; transitions between them are shown in figure 67. * * * * STS wait state (serial interface 2 is in SM2A read wait state) Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode)
System reset
00
STS instruction wait state (with octal counter = 000, transmit clock disabled)
SM1A write
04
STS instruction*
01 02
SM1A write (IFS1 1)
06
Transmit clock Transmit clock wait state (octal counter = 000)
Transfer state (octal counter 000) Eight transmit clock cycles STS instruction* 05 (IFS1 1) External Clock Mode 03
System reset SM1A write Transmit clock continuous output state (PMRA 0, 1 = 00) Transmit clock 17
10 18
STS instruction wait state (with octal counter = 000, transmit clock disabled)
SM1A write
14 STS instruction* 11
Eight transmit clock cycles STS instruction 16 (IFS1 1)
13
Transmit clock 12 Transmit clock wait state (octal counter = 000) STS instruction * 15 (IFS1 1) Internal Clock Mode Note: * For serial interface 2, this is accomplished by reading the SM2A register. Circled numbers are referred to in the text.
Transfer state (octal counter 000)
Figure 67 Serial Interface State Transition Diagram The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1. * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state.
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HD404639R Series
* Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and puts the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state and when serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin, SO1 and SO2, can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1, or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example of serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state.
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Transmit clock wait state State MCU reset Port selection PMRA write External clock selection SM1A write Output level control in idle states SM1B write Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB MSB Dummy write for state transition Output level control in idle states STS wait state Transfer state Transmit clock wait state STS wait state
IFS1 External clock mode Transmit clock wait state State MCU reset Port selection PMRA write Internal clock selection SM1A write Output level control in idle states SM1B write SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin Undefined LSB MSB Data write for transmission Output level control in idle states STS wait state Transfer state STS wait state Flag reset at transfer completion
IFS1 Internal clock mode Flag reset at transfer completion
Figure 68 Example of Serial Interface 1 Operation Sequence
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HD404639R Series
Transmit Clock Error Detection (In External Clock Mode): Each serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 69. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS1 is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag is set again, and therefore the error can be detected. The same applies to serial interface 2.
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HD404639R Series
IFS1 = 1 State Transmit clock wait state Transfer state SCK 1 pin (input) Noise 1 2 3 4 SM1A write IFS1
Transfer completion (IFS1 1)
Interrupts inhibited
IFS1 0
SM1A write
Yes
Transmit clock error processing
No
Normal termination
Transmit clock error detection flowchart
Transmit clock wait state Transfer state
5
6
7 8 Transfer state has been entered by the transmit clock error. When SM1A is written,IFS1 is set.
Flag set because octal counter reaches 000. Transmit clock error detection procedures
Flag reset at transfer completion.
Figure 69 Transmit Clock Error Detection
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HD404639R Series
Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) and serial mode register 2A (SM2A: $01B) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) and serial 2 interrupt request flag (IFS2: $023, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (IFS1: $003, bit 2) is not set. In the same way for serial interface 2, if the state is changed from transfer state to another by writing to serial mode register 2A (SM2A: $01B) or by executing the STS instruction during the first low pulse of the transmit clock, the serial 2 interrupt request flag is not set. To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. To set the serial 2 interrupt request flag, a serial mode register 2A write or SM2A instruction execution must be programmed to be executed after confirming that the SCK 2 pin is at 1, that is, after executing the input instruction to port R5. Registers for Serial Interface When serial interface operation is selected, serial data is read and written by the following registers. For serial interface 1 * * * * * Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Serial data register 1 (SR1L: $006, SR1U: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C)
For serial interface 2 * * * * Serial mode register 2A (SM2A: $01B) Serial mode register 2B (SM2B: $01C) Serial data register 2 (SR2L: $01D, SR2U: $01E) Port mode register A (PMRA: $004)
Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 70). * * * * R4 1/SCK 1 pin function selection Serial interface 1 transmit clock selection Serial interface 1 prescaler division ratio selection Serial interface 1 initialization
Serial mode register 1A is a 4-bit write-only register. It is reset to $0 by MCU reset.
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HD404639R Series
A write signal input to serial mode register 1A discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.
Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output
Clock source Prescaler
Prescaler division ratio Refer to table 27
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 70 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 71). * Serial interface 1 prescaler division ratio selection * Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO 1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to.
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HD404639R Series
Serial mode register 1B (SM1B: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- --
1 Undefined W
0 0 W SM1B0
Not used Not used SM1B1
SM1B1 0 1
Output level control in idle states Low level High level
SM1B0 0 1
Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4
Figure 71 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 72 and 73) * Serial interface 1 transmission data write and shift * Serial interface 1 receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 74. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register 1 (lower digit) (SR1L: $006) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR13 R/W SR12 R/W SR11 R/W SR10
Figure 72 Serial Data Register 1 (SR1L)
Serial data register 1 (upper digit) (SR1U: $007) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR17 R/W SR16 R/W SR15 R/W SR14
Figure 73 Serial Data Register 1 (SR1U)
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HD404639R Series
Transmit clock 1 Serial output data LSB 2 3 4 5 6 7 8 MSB
Serial input data latch timing
Figure 74 Serial Interface Output Timing
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HD404639R Series
Port Mode Register A (PMRA: $004): This register has the following functions (figure 75). * * * * R4 2/SI 1 pin function selection R4 3/SO 1 pin function selection R5 2/SI 2 pin function selection R5 3/SO 2 pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W
PMRA2 PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1 PMRA2 0 1 PMRA3 0 1
R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1 R53/SO2 mode selection R53 SO2 R52/SI2 mode selection R52 SI2
Figure 75 Port Mode Register A (PMRA) Miscellaneous Register (MIS: $00C): This register has the following functions (figure 76). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
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HD404639R Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS1 0
MIS0 0
tRC 0.12207 ms 0.24414 ms*
1 1 0 1 MIS2 0 1 MIS3 0 1
7.8125 ms 31.25 ms Not used
R43/SO1 PMOS on/off selection On Off Pull-up MOS on/off selection Off On
Note: * This value is valid only for direct transfer operation.
Figure 76 Miscellaneous Register (MIS) Serial Mode Register 2A (SM2A: $01B): This register has the following functions (figure 77). * * * * R5 1/SCK 2 pin function selection Serial interface 2 transmit clock selection Serial interface 2 prescaler division ratio selection Serial interface 2 initialization
Serial mode register 2A (SM2A: $01B) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 2A discontinues the input of the transmit clock to serial data register 2 (SR2L: $01D, SR2U: $01E) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the SM2A read instruction must be executed at least two cycles after that.
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HD404639R Series
Serial mode register 2A (SM2A: $01B) Bit Initial value Read/Write Bit name 3 0 W SM2A3 2 0 W SM2A2 1 0 W SM2A1 0 0 W SM2A0
SM2A3 0 1
R51/SCK2 mode selection R51 SCK2
SM2A2 0
SM2A1 0
SM2A0 0 1
SCK2 Output
Clock source Prescaler
Prescaler division ratio Refer to table 27
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 77 Serial Mode Register 2A (SM2A) Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78). * Serial interface 2 prescaler division ratio selection * Serial interface 2 output level control in idle states * R5 3/SO 2 pin PMOS control Serial mode register 2B is a 3-bit write-only register. It cannot be written during serial interface 2 data transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) are reset to $0 by MCU reset. By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is selected. By resetting bit 1 (SM2B1), the output level of the SO2 pin is controlled in idle states of serial interface 2. The output level changes at the same time that SM2B1 is written to.
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HD404639R Series
Serial mode register 2B (SM2B: $01C) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W
1 Undefined W SM2B1
0 0 W SM2B0
Not used SM2B2
SM2B2 0 1
R53 /SO 2 PMOS On Off
SM2B0 0 1 SM2B1 0 1
Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4 Output level control in idle states Low level High level
Figure 78 Serial Mode Register 2B (SM2B) Serial Data Register 2 (SR2L: $01D, SR2U: $01E): This register has the following functions (figures 79 and 80). * Serial interface 2 transmission data write and shift * Serial interface 2 receive data shift and read Writing data in this register is output from the SO2 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI2 pin at the rising edge of the transmit clock. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register 2 (lower digit) (SR2L: $01D) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR23 R/W SR22 R/W SR21 R/W SR20
Figure 79 Serial Data Register 2 (SR2L)
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HD404639R Series
Serial data register 2 (upper digit) (SR2U: $01E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR27 R/W SR26 R/W SR25 R/W SR24
Figure 80 Serial Data Register 2 (SR2U)
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HD404639R Series
DTMF Generator Circuit
The MCU provides a dual-tone multifrequency (DTMF) generator circuit. The DTMF signal consists of two sine waves to access the switching system. Figure 81 shows the DTMF keypad and frequencies. Each key enables tones to be generated corresponding to each frequency. Figure 82 shows a block diagram of the DTMF circuit. The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz or 8 MHz) is changed into six clock signals through the division circuit (1/2, 1/5, 1/9, 1/10, 1/18 and 1/20). The DTMF circuit uses one of the six clock signals, which is selected by system clock select register 1 (SSR1: $029) and system clock select register 2 (SSR2: $02A) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers, sine wave counters, and control registers. The DTMF generator circuit is controlled by the following three registers.
1
2
3
A
R1 (697 Hz) R2 (770 Hz) R3 (852 Hz) R4 (941 Hz)
4
5
6
B
7
8
9
C
* C1 (1,209 Hz)
0 C2 (1,336 Hz)
# C3 (1,477 Hz)
D C4 (1,633 Hz)
Figure 81 DTMF Keypad and Frequencies
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HD404639R Series
TONER Sine wave counter D/A Feedback VT ref Transformation program divider 2
TONER output control
Tone generator mode register (TGM)
Feedback
2
TONEC output control 2 f OSC 400 kHz 800 kHz 1/2 2 MHz 1/5 3.58 MHz 4 MHz 1/10 7.16 MHz*2 8 MHz*2 1/20 1 1/18*3 System clock selection register 2 (SSR2) *1 1/9*3 Selector 400 kHz *3 System clock selection register 1 (SSR1)
Notes: 1. System clock selection register 2 (SSR2) is used to specify the divide-by-9 or divide-by-18 operation when a 3.58-MHz or 7.16 MHz system clock oscillator is used. 2. Applies to HD40A4638R, HD40A4639R and HD407A4639R. 3. This is 397.8 kHz when fOSC is 3.58 MHz and 7.16 MHz.
Figure 82 Block Diagram of DTMF Generator Circuit
Internal data bus
TONEC
Sine wave counter D/A
Transformation program divider
Tone generator control register (TGC)
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HD404639R Series
Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output frequencies as shown in figure 83, and is reset to $0 by MCU reset.
Tone generator mode register (TGM: $019) Bit Initial value Read/Write Bit name 3 0 W TGM3 2 0 W TGM2 1 0 W TGM1 0 0 W TGM0
TGM3 0 0 1 1
TGM2 0 1 0 1
TONEC output frequencies f C1 (1,209 Hz) f C2 (1,336 Hz) f C3 (1,477 Hz) f C4 (1,633 Hz)
TGM1 0 0 1 1
TGM0 0 1 0 1
TONER output frequencies f R1 (697 Hz) f R2 (770 Hz) f R3 (852 Hz) f R4 (941 Hz)
Figure 83 Tone Generator Mode Register (TGM) Tone Generator Control Register (TGC: $01A): Three-bit write-only register, which controls the start/stop of the DTMF signal output as shown in figure 84, and is reset to $0 by MCU reset. TONER and TONEC output can be independently controlled by bits 2 and 3 (TGC2, TGC3), and the DTMF circuit is controlled by bit 1 (TGC1) of this register.
Tone generator control register (TGC: $01A) Bit Initial value Read/Write Bit name 3 0 W TGC3 2 0 W TGC2 1 0 W TGC1 0 -- -- Not used
TGC3 0 1 TGC2 0 1
TONEC output control (column) No output TONEC output (active) TONER output control (row) No output TONER output (active)
TGC1 0 1
DTMF enable bit DTMF disable DTMF enable
Figure 84 Tone Generator Control Register (TGC)
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HD404639R Series
System Clock Select Registers 1 and 2 (SSR1: $029, SSR2: $02A): Four-bit write-only registers. These registers must be set to the value specified in figures 85 and 86 depending on the frequency of the oscillator connected to the OSC1 and OSC2 pins. Note that if the combination of the oscillation frequency and the values in these registers is different from that specified in figures 85 and 86, the DTMF output frequencies will differ from the correct frequencies as listed in table 28.
System clock select register 1 (SSR1: $029) Bit Initial value Read/Write Bit name 3 0 W SSR13 2 0 W SSR12 1 0 W SSR11 0 0 W SSR10
SSR13 32-kHz oscillation stop 0 1 Oscillation operates in stop mode Oscillation stops in stop mode
System clock SSR23 SSR22 SSR11 SSR10 selection 0 0 0 0 1 400 kHz 800 kHz 2 MHz 4 MHz
32-kHz oscillation division SSR12 ratio selection 0 1 f SUB = f X /8 f SUB = f X /4 1 1 0 1
1
0 1
Don't care Don't care 3.58 MHz 1 1 8 MHz
Don't care Don't care 7.16 MHz
Figure 85 System Clock Select Register 1(SSR1)
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HD404639R Series
Serial clock select register 2 (SSR2: $02A) Bit Initial value Read/Write Bit name 3 0 W SSR23 2 0 W SSR22
1 0 W SSR21
0 0 W SSR20
SSR23 SSR22 System clock selection 0 0 1 1 0 1 Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz * 1 3.58 MHz 8 MHz
*1
SSR21 SSR20 System clock division ratio 0 0 1 1 0 1 1/4 division 1/8 division 1/16 division 1/32 division
7.16 MHz
Notes: 1. Refer to system clock select register 1 (SSR1) of figure 85. 2. The DTMF frequencies are not affected by the setting of the system clock division ratio.
Figure 86 System Clock Select Register 2(SSR2) Table 28 Frequency Deviation of the MCU from Standard DTMF
fOSC = 400 kHz, 800 kHz, 2 MHz, 4 MHz, 8 MHz Standard DTMF (Hz) R1 R2 R3 R4 C1 C2 C3 C4 697 770 852 941 1,209 1,336 1,477 1,633 MCU (Hz) 694.44 769.23 851.06 938.97 1,212.12 1,333.33 1,481.48 1,639.34 Deviation from Standard (%) -0.37 -0.10 -0.11 -0.22 0.26 -0.20 0.30 0.39 fOSC = 3.58 MHz, 7.16 MHz Deviation from Standard (%) -0.92 -0.65 -0.67 -0.77 -0.30 -0.75 -0.25 -0.17
MCU (Hz) 690.58 764.96 846.33 933.75 1,205.39 1,325.92 1,473.25 1,630.23
Note: This frequency deviation value does not include the frequency deviation due to the oscillator element. Also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50%:50%.
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HD404639R Series
DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER, TONEC) transmit the sine waves of the row-group and column-group, respectively. Figure 87 shows the tone output equivalent circuit. Figure 88 shows the output waveform. One cycle of this wave consists of 32 slots. Therefore, the output waveform is stable with little distortion. Table 28 lists the frequency deviation of the MCU from standard DTMF signals.
Switch control VTref GND
TONER TONEC
Figure 87 Tone Output Equivalent Circuit
VTref
1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32
GND Time slots
Figure 88 Waveform of Tone Output
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HD404639R Series
Comparator
The block diagram of the comparator is shown in figure 89. The comparator compares input voltage with the reference voltage. Internal voltage or external input voltage can be selected as the reference. Internal reference voltage is selected from sixteen levels. Setting bit 3 (CER3) of the compare enable register (CER: $018) to 1 executes a voltage comparison. When an input voltage at COMP0-COMP3 is higher than the reference voltage, the TM or TMD command sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to COMP0-COMP3. On the other hand, when an input voltage at COMP0-COMP3 is lower, the TM or TMD command clears the ST to 0.
COMP0 COMP1 COMP2 COMP3 VCref Selector + - Comparator
Comparator data register (CDR)
Selector
2 5R R R Comparator enable register (CER)
R 2R 4 Comparator control register (CCR)
Selector
Figure 89 Block Diagram of Comparator Compare Enable Register (CER: $018): Four-bit write-only register which enables comparator operation, and selects the reference voltage and the analog input pin. Compare Control Register (CCR: $016): Four-bit write-only register which selects the internal reference voltage from sixteen levels. Compare Data Register (CDR: $017): Four-bit read-only register which latches the result of the comparison between the analog input pins and the reference voltage. Bits 0 to 3 show the results of comparison with COMP 0 -COMP 3 , respectively. This register can be read only by the TM or TMD
104
Internal data bus
HD404639R Series
command. Only bit CER3 corresponds to the analog input pin selected with bits CER0 and CER1. After a compare operation, the data in this register is not retained. Note on Use: During the compare operation pins RD0/COMP0-RD3/COMP3 operate as analog inputs and cannot operate as R ports. The comparator can operate in active mode and subactive mode but is disabled in other modes. The switch for the internal reference voltage is on only when the internal reference voltage is selected by CER2. RE0/VC ref cannot operate as an R port when the external input voltage is selected as the reference.
Compare enable register (CER: $018) Bit Initial value Read/Write Bit name 3 0 W CER3 2 0 W CER2 1 0 W CER1 0 0 W CER0
CER3 0
Digital/Analog selection Digital input mode: RD0 /COMP0-RD3 /COMP3 operate as R port Analog input mode: RD0 /COMP0-RD3 /COMP3 operate as analog input Reference voltage selection External input voltage Internal voltage
CER1 0
CER0 0 1
Analog input pin selection COMP0 COMP1 COMP2 COMP3
1
1
0 1
CER2 0 1
Figure 90 Compare Enable Register (CER)
105
HD404639R Series
Compare control register (CCR: $016) Bit Initial value Read/Write Bit name 3 0 W CCR3 2 0 W CCR2 1 0 W CCR1 0 0 W CCR0
CCR3 0
CCR2 0
CCR1 0
CCR0 0 1
Reference voltage selection 2/22 VCC 3/22 VCC 4/22 VCC 5/22 VCC 6/22 VCC 7/22 VCC 8/22 VCC 9/22 VCC 10/22 VCC 11/22 VCC 12/22 VCC 13/22 VCC 14/22 VCC 15/22 VCC 16/22 VCC 17/22 VCC
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Figure 91 Compare Control Register (CCR)
106
HD404639R Series
Compare data register (CDR: $017) Bit Initial value Read/Write Bit name 3 R CDR3 2 R CDR2 1 R CDR1 0 R CDR0 Result of COMP0 comparison Result of COMP1 comparison Result of COMP2 comparison Result of COMP3 comparison
Undefined Undefined Undefined Undefined
Figure 92 Compare Data Register (CDR)
107
HD404639R Series
Programmable ROM (HD407A4639R)
The HD407A4639R is a ZTATTM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description
MCU Mode Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name RD0/COMP0 RD1/COMP1 RD2/COMP2 RD3/COMP3 RE 0/VCref TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12/STOPC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I A13 A14 A9 I I I I/O I I I I I I I O I I O GND CE OE VCC VCC I I RESET GND I GND TEST VCC I PROM Mode Pin Name I/O Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MCU Mode Pin Name D13/INT0 R0 0/INT1 R0 1/INT2 R0 2/INT3 R0 3/INT4 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0/TOB R3 1/TOC R3 2/TOD R3 3/EVNB R4 0/EVND R4 1/SCK 1 R4 2/SI1 R4 3/SO 1 R5 0 R5 1/SCK 2 R5 2/SI2 R5 3/SO 2 PROM Mode I/O Pin Name I VPP I I I/O
I/O M0 I/O M1 I/O I/O I/O A5 I/O A6 I/O A7 I/O A8 I/O A0 I/O A10 I/O A11 I/O A12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I I I I I I I I
108
HD404639R Series
MCU Mode Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Pin Name R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name A1 A2 A3 A4 O0 O1 O2 O3 O4 O5 O6 O7 O4 O3 O2 I/O Pin No. I I I I 66 67 68 69 MCU Mode Pin Name R9 3 RA 0 RA 1 RA 2 RA 3 RB 0 RB 1 RB 2 RB 3 RC0 SEL TONEC TONER VCC VT ref PROM Mode I/O Pin Name I/O O1 I/O O0 I/O VCC I/O I/O I/O I/O I/O I/O I/O I O O VCC VCC I/O I/O I/O
I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using, each pair must be connected together.
Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 93. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD407A4639 are listed in table 30. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed.
109
HD404639R Series
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTATTM devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 29. Table 29 PROM Mode Selection
Pin Mode Programming Verification Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0-O7 Data input Data output High impedance
Table 30 Recommended PROM Programmers and Socket Adapters
PROM Programmer Manufacturer DATA I/O Corp. AVAL Corp. Model Name 121B PKW-1000 Socket Adapter Package FP-80B Manufacturer Hitachi Model Name HS463ESF01H
110
HD404639R Series
VCC VCC RESET TEST M0 M1 O0 to O7 VPP VCC OSC1 D2 D3 RA1 VT ref VCref X1 OE CE OE CE HD407A4639R A0 to A14 Address A0 to A14 Data O0 to O7 VCC
VPP
GND
Figure 93 PROM Mode Connections
111
HD404639R Series
Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 94 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
W register W1 W0
X3
X register
X2 X1 X0 Y3
Y register
Y2 Y 1
Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction
d8 d7 d6 d5 d4 d3 d2 d1
d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0
m3 m2
m1
m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 94 RAM Addressing Modes
112
HD404639R Series
ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 95 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 97. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 96. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
113
HD404639R Series
[JMPL] [BRL] [CALL] 1st word of instruction Opcode
p3 p2 p1 p0
2nd word of instruction d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing
Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing
Instruction [CAL] 0 Program counter 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1
Accumulator B0 A3 A2 A1 A0
0
0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 95 ROM Addressing Modes
114
HD404639R Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
B3
B2
B1
B0
B3
B2
B1
B0
If RO 9 = 1
Pattern Output
Figure 96 P Instruction
115
HD404639R Series
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 97 Branching when the Branch Destination is on a Page Boundary
116
HD404639R Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Symbol VCC VPP VT Io -Io Io Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to VCC + 0.3 105 50 4 30 Maximum output current -I o 4 20 Operating temperature Storage temperature Topr Tstg -20 to +75 -55 to +125 Unit V V V mA mA mA mA mA mA C C 2 3 4, 5 4, 6 7, 8 7, 9 1 Note
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 13 (VPP) of HD407A4639R. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to GND. 5. Applies to D 0-D 3, and R0-RC. 6. Applies to D 4-D 11 . 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 4-D 11 and R0-RC. 9. Applies to D 0-D 3.
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HD404639R Series
Electrical Characteristics
DC Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pin(s) RESET, STOPC, INT0 -INT4,SCK 1 SI 1, SCK 2, SI 2, EVNB, EVND OSC 1 Input low voltage VIL RESET, STOPC, INT0 -INT4, SCK 1 SI 1, SCK 2, SI 2, EVNB, EVND OSC 1 Output high VOH voltage Output low VOL voltage I/O leakage | IIL | current SCK 1, SO1, SCK 2, SO2, TOB, TOC, TOD SCK 1, SO1, SCK 2, SO2, TOB, TOC, TOD RESET, STOPC, INT0 -INT4, SCK 1, SI 1, SCK 2, SI 2, SO1, SO2, EVNB, EVND, OSC 1, TOB, TOC, TOD VCC Min 0.9V CC Typ -- Max VCC + 0.3 Unit V Test Condition Notes
VCC - 0.3 -0.3
-- --
VCC + 0.3 0.10 VCC
V V
External clock
-0.3 VCC - 1.0
-- --
0.3 --
V V
External clock -I OH = 0.5 mA
--
--
0.4
V
I OL = 0.4 mA
--
--
1
A
Vin = 0 V to VCC
1
I CC1 Current dissipation in active mode I CC2
--
2.5
5
mA
VCC = 5 V, 2 f OSC = 4 MHz, digital input mode VCC = 3 V, 2 f OSC = 800 kHz, digital input mode VCC = 5 V, 2, 8 f OSC = 8 MHz, digital input mode VCC = 5 V, f OSC = 4 MHz, analog comp. mode 3
VCC
--
0.3
1.0
mA
I CC3
VCC
--
5
9
mA
I CMP1
VCC
--
6.5
9
mA
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HD404639R Series
Item Symbol Pin(s) VCC Min -- Typ 2.8 Max 3.5 Unit mA Test Condition VCC = 3 V, f OSC = 800 kHz, analog comp. mode VCC = 5 V, f OSC = 8 MHz, analog comp. mode VCC = 5 V, f OSC = 4 MHz Notes 3 I CMP2 Current dissipation in active mode I CMP3
VCC
--
9
13
mA
3, 8
I SBY1 Current dissipation in standby mode I SBY2 I SBY3 I SUB Current dissipation in subactive mode I WTC Current dissipation in watch mode I STOP Current dissipation in stop mode Stop mode VSTOP retaining voltage Comparator VC ref input reference voltage scope Allowable error of internal reference voltage VOFS
VCC
--
1.0
2
mA
4
VCC VCC VCC
-- -- --
0.1 2.0 18
0.3 4.0 35
mA mA A
VCC = 3 V, f OSC = 800 kHz VCC = 5 V, f OSC = 8 MHz VCC = 3 V, 32 kHz oscillator
4 4, 8 5
VCC
--
4
7.5
A
VCC = 3 V, 32 kHz oscillator
5
VCC
--
0.5
5
A
VCC = 3 V, no 32 kHz oscillator No 32 kHz oscillator
5
VCC
2
--
--
V
6
VC ref
0
--
VCC - 1.2
V
-100
--
100
mV
VOFS = reference voltage - VC ref
7
Notes: 1. Output buffer current is excluded. 2. I CC1, I CC2 and I CC3 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at V CC (VCC -0.3 to VCC) TEST at V CC (VCC -0.3 to VCC)
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HD404639R Series
3. RD0-RD3 pins are in analog input mode when no I/O current is flowing. Test conditions: MCU: DTMF does not operate Pins: RD0/COMP0 at GND (0 V to 0.3 V) RD1/COMP1 at GND (0 V to 0.3 V) RD2/COMP2 at GND (0 V to 0.3 V) RD3/COMP3 at GND (0 V to 0.3 V) RE 0/VCref at GND (0 V to 0.3 V) 4. I SBY1, I SBY2 and I SBY3 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped DTMF does not operate Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC -0.3 to VCC) 5. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC -0.3 to VCC) D13* at VCC (VCC -0.3 to VCC) * Applies to HD407A4639R. 6. RAM data retention. 7. The reference voltage is the expected internal VC ref voltage selected by the compare control register (CCR: $016). Example: when CCR = $2, reference voltage is 4/22 x VCC. 8. Applies to HD40A4638R, HD40A4639R, HD407A4639R.
120
HD404639R Series
I/O Characteristics for Standard Pins (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: VCC = 2.7 to 5.5 V, GND = 0 V, T a = - 20 to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Symbol VIH VIL VOH VOL |I IL| Pin(s) Min Typ -- -- Max VCC + 0.3 0.3V CC -- 0.4 1 1 1 20 90 Unit V V V V A A A A A V V -I OH = 0.5 mA I OL = 0.4 mA Vin = 0 V to VCC Vin = 0 V to VCC 1 1, 2 Test Condition Notes
D12-D 13 , 0.7 VCC R0-RD, RE0 D12-D 13 , -0.3 R0-RD, RE0 R0-RC R0-RC D12, R0-RD RE 0, D13
VCC -1.0 -- -- -- -- -- -- -- -- -- -- -- 30
Vin = VCC - 0.3 V to VCC 1, 3 Vin = 0 V to 0.3 V VCC = 3 V, Vin = 0 V Analog compare mode Analog compare mode 1, 3
Pull-up MOS -I PU current Input high voltage Input low voltage VIHA VILA
R0-RC
5
COMP0- COMP3 COMP0- COMP3
VC ref+0.1 -- -- --
-- VC ref -0.1
Notes: 1. Output buffer current is excluded. 2. Applies to HD404638R, HD404639R, HD40A4638R and HD40A4639R. 3. Apples to HD407A4639R.
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HD404639R Series
I/O Characteristics for High-Current Pins (HD404638R, HD404639R, HD40A4638R, HD40A4639R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: V CC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Symbol VIH VIL VOH Pin(s) D0-D 11 D0-D 11 D0-D 11 D0-D 3 Output low voltage VOL D0-D 11 D4-D 11 I/O leakage current |I IL| D0-D 11 D4-D 11 D0-D 3 Min 0.7 VCC -0.3 Typ -- -- Max VCC + 0.3 0.3 VCC -- -- 0.4 2.0 1 90 90 Unit V V V V V V A A A -I OH = 0.5 mA, -I OH = 10 mA, VCC = 4.5 V to 6.0 V I OL = 0.4 mA I OL = 15 mA, VCC = 4.5 V to 6.0 V Vin = 0 V to VCC VCC = 3 V, Vin = 0 V VCC = 3 V, Vin = 3 V 1 2 1 Test Condition Notes
VCC - 1.0 -- 2.0 -- -- -- 5 5 -- -- -- -- 30 30
Pull-up MOS -I PU current Pull-down I PD MOS current
Notes: 1. HD407A4639R; V CC = 4.5 V to 5.5 V 2. Output buffer current is excluded.
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HD404639R Series
DTMF Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Tone output voltage (1) Tone output voltage (2) Tone output distortion Tone output ratio Symbol VOR VOC %DIS Pin(s) TONER TONEC Min 500 520 -- Typ 660 690 3 Max -- -- 7 Unit Test Condition Notes 1 1 2
mVrms VT ref - GND = 2.0 V, RL = 100 k mVrms VT ref - GND = 2.0 V, RL = 100 k % Short circuit between TONER and TONEC RL = 100 k Short circuit between TONER and TONEC RL = 100 k
dBCR
--
2.5
--
dB
2
Notes: 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4MHz, 7.16 MHz, or 8 MHz can be used as the operating trequency (f OSC). 1. See figure 98. 2. See figure 99.
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HD404639R Series
AC Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified)
Item Symbol Pin(s) OSC 1, OSC 2 Min -- -- -- -- -- -- -- X1, X2 Instruction cycle t cyc time -- -- -- -- -- t subcyc -- -- Oscillation t RC stabilization time (ceramic) Oscillation t RC stabilization time (crystal) OSC 1, OSC 2 OSC 1, OSC 2 -- Typ 400 800 2 3.58 4 7.16 8 32.768 8 4 2 1 244.14 122.07 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7.5 Unit kHz kHz MHz MHz MHz MHz MHz kHz s s s s s s ms f OSC = 4 MHz, 1/32 division f OSC = 4 MHz, 1/16 division f OSC = 4 MHz, 1/8 division f OSC = 4 MHz, 1/4 division 32 kHz oscillator, 1/8 division 32 kHz oscillator, 1/4 division 2 2 2 2 3 3 4, 5 Test Condition Notes 1 1 1 1 1 1, 12 1, 12
Clock oscillation f OSC frequency
--
--
40
ms
VCC = 3.5 V to 6.0 V
4, 5, 6
-- X1, X2 External clock high width t CPH OSC 1 -- 1100 550 215 115 105 57.5 52.5
-- -- -- -- -- -- -- -- --
60 3 -- -- -- -- -- -- --
ms s ns ns ns ns ns ns ns Ta = -10C to +60C f OSC = 400 kHz f OSC = 800 kHz f OSC = 2 MHz f OSC = 3.58 MHz f OSC = 4 MHz f OSC = 7.16 MHz f OSC = 8 MHz
4, 5 4 7 7 7 7 7 7, 12 7, 12
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HD404639R Series
Item External clock low width Symbol t CPL Pin(s) OSC 1 Min 1100 550 215 115 105 57.5 52.5 External clock rise time t CPr OSC 1 -- -- -- -- -- -- -- External clock fall time t CPf OSC 1 -- -- -- -- -- -- -- INT0-INT4, EVNB, EVND high width INT0-INT4, EVNB, EVND low width RESET high width STOPC low width RESET fall time t IH INT0- INT4, EVNB, EVND INT0- INT4, EVNB, EVND RESET STOPC RESET STOPC 2 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 150 75 35 25 20 12.5 10 150 75 35 25 20 12.5 10 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t cyc / t subcyc Test Condition f OSC = 400 kHz f OSC = 800 kHz f OSC = 2 MHz f OSC = 3.58 MHz f OSC = 4 MHz f OSC = 7.16 MHz f OSC = 8 MHz f OSC = 400 kHz f OSC = 800 kHz f OSC = 2 MHz f OSC = 3.58 MHz f OSC = 4 MHz f OSC = 7.16 MHz f OSC = 8 MHz f OSC = 400 kHz f OSC = 800 kHz f OSC = 2 MHz f OSC = 3.58 MHz f OSC = 4 MHz f OSC = 7.16 MHz f OSC = 8 MHz Notes 7 7 7 7 7 7, 12 7, 12 7 7 7 7 7 7, 12 7, 12 7 7 7 7 7 7, 12 7, 12 8
t IL
2
--
--
t cyc / t subcyc
8
t RSTH t STPL t RSTf
2 1 -- --
-- -- -- --
-- -- 20 20
t cyc t RC ms ms
9 10 9 10
STOPC rise time t STPr
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HD404639R Series
Item Input capacitance Symbol Cin Pin(s) All pins except D13 D13 D13 Analog t CSTB comparator stabilization time Min -- Typ -- Max 15 Unit pF Test Condition f = 1 MHz, Vin = 0 V Notes
-- --
-- -- --
15 180 2
pF pF t cyc
f = 1 MHz, Vin = 0 V f = 1 MHz, Vin = 0 V
13 14 11
COMP0- -- COMP3
Notes: Except for the HD407A4639R, when V CC is between 2.2 V and 6.0 V, watch mode can be supported, and instruction execution is possible in active mode. 1. Bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) must be set according to the system clock frequency. 2. Bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A) must be set according to the division ratio of the system clock frequency. 3. Bit 2 (SSR12) of system clock select register 1 (SSR1: $029) must be set according to the division ratio of the subsystem clock frequency. 4. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) according to the system oscillation of the oscillation stabilization time. 5. Bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) must be set according to the oscillation stabilization time of the system clock oscillator. 6. HD407A4639R: V CC = 3.5 V to 5.5 V. 7. Refer to figure 100. 8. Refer to figure 101. The t cyc unit applies when the MCU is in standby or active mode. The tsubcyc unit applies when the MCU is in watch or subactive mode. 9. Refer to figure 102. 10. Refer to figure 103. 11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering RD 0/COMP0-RD3/COMP3 into analog input mode. 12. Applies to HD40A4638R, HD40A4639R and HD407A4639R. HD40A4638R, HD40A4639R: VCC = 4.5 V to 6.0 V HD407A4639R: V CC = 4.5 V to 5.5 V 13. Applies to HD404638R, HD404639R, HD40A4638R and HD40A4639R. 14. Applies to HD407A4639R.
126
HD404639R Series
Serial Interface Timing Characteristics (HD404638R, HD404639R, HD40A4638R, HD40A4639R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C; HD407A4639R: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Symbol t Scyc Pin(s) SCK 1, SCK 2 Test Condition Load shown in figure 105 Min 1 Typ -- Max -- Unit t cyc Notes 1
t SCKH
SCK 1, SCK 2
Load shown in figure 105
0.5
--
--
t Scyc
1
t SCKL
SCK 1, SCK 2
Load shown in figure 105
0.5
--
--
t Scyc
1
t SCKr
SCK 1, SCK 2
Load shown in figure 105
--
--
200
ns
1
Transmit t SCKf clock fall time Serial output t DSO data delay time Serial input data setup time Serial input data hold time t SSI
SCK 1, SCK 2 SO1, SO 2
Load shown in figure 105 Load shown in figure 105
-- --
-- --
200 500
ns ns
1 1
SI 1, SI2
300
--
--
ns
1
t HSI
SI 1, SI2
300
--
--
ns
1
127
HD404639R Series
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Symbol t Scyc Pin(s) SCK 1, SCK 2 Test Condition Min 1 Typ -- Max -- Unit t cyc Notes 1
t SCKH
SCK 1, SCK 2
0.5
--
--
t Scyc
1
t SCKL
SCK 1, SCK 2
0.5
--
--
t Scyc
1
t SCKr
SCK 1, SCK 2
--
--
200
ns
1
Transmit t SCKf clock fall time Serial output t DSO data delay time Serial input data setup time Serial input data hold time Note: t SSI
SCK 1, SCK 2 SO1, SO 2 Load shown in figure 105
-- --
-- --
200 500
ns ns
1 1
SI 1, SI2
300
--
--
ns
1
t HSI
SI 1, SI2
300
--
--
ns
1
1. Refer to figure 104.
RL = 100 k TONEC
RL = 100 k TONER GND
Figure 98 TONE Output Load Circuit
128
HD404639R Series
TONEC RL = 100 k
TONER GND
Figure 99 Distortion dBCR Load Circuit
OSC 1
1/fCP VCC - 0.3 V 0.3 V tCPH tCPr tCPf tCPL
Figure 100 External Clock Timing
INT0 -INT4, EVNB, EVND
0.9 VCC 0.1 VCC
t IH
t IL
Figure 101 Interrupt Timing
RESET
0.9 VCC
0.1 VCC
tRSTH
tRSTf
Figure 102 Reset Timing
129
HD404639R Series
STOPC
0.9 VCC 0.1 V CC
tSTPL tSTPr
Figure 103 STOPC Timing
t Scyc t SCKf SCK 1 SCK 2 V CC- 1.0 V (0.9 VCC )* 0.4 V (0.1 VCC )* t DSO SO 1 SO 2 VCC - 0.5 V 0.4 V t SSI SI 1 SI 2 0.9 V CC 0.1 V CC t HSI t SCKL t SCKH t SCKr
Note: * VCC - 1.0 V and 0.4 V are the threshold voltages for transmit clock output. 0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock output.
Figure 104 Serial Interface Timing
VCC RL = 2.6 k Test point C 30 pF R 12 k 1S2074 H or equivalent
Figure 105 Timing Load Circuit
130
HD404639R Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404639R, HD40A4639R). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base.
ROM 8-kword version: HD404638R, HD40A4638R Address $2000-$3FFF
$0000 Vector address (16 words) $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF Fill this area with 1s
131
HD404639R Series
HD404638/HD404639/HD404638R/HD404639R/HD40A4638R/HD40A4639R Option List Please check off the appropriate applications and enter the necessary information. 1. ROM Size
Standaed version : HD404638 Standard version : HD404638R High-speed version : HD40A4638R Standard version : HD404639 Standard version : HD404639R High-speed version : HD40A4639R ROM 16-kword ROM 8-kword Date of order Customer Department Name ROM code name LSI number / /
2. Optional Functions
* * * With 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base
Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).
3. ROM Code Media Please specify the first type listed below (the upper bits and lower bits are mixed together) when using the EPROM on-package microcomputer type (including ZTATTM version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper bits and lower five bits are programmed to different EPROMs.
4. Oscillator for OSC1 and OSC2
Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Stop Mode
Used Not used
6. Package
FP-80B
132
HD404639R Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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